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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History
Revision No.
0.0 Initial Draft.
History
Draft Date
Sep. 2004
Remark
Preliminary
0.1
1) Correct part number ( change mode) - 2A -> 1A (sequential row read : disable -> enable) 2) Correct Table.5 & Table 12 - Correct Command Set - correct AC timing characteristics (tWP : 40 -> 25ns, tWH : 20 ->15ns) 3) Correct Summary description & page.7 - The cache feature is deleted in summary description. Oct. 22. 2004 - Note.3 is deleted. (page.7) 4) Add System interface using CE don't care (page. 38) 5) Change TSOP1, WSOP1,FBGA package dimension & figures. - Change TSOP1, WSOP1, FBGA package mechanical data - Change TSOP1, WSOP package figures 6) Correct TSOP1, WSOP1 Pin configuration - 38th NC pin has been changed Lockpre (figure 2,3) 7) Add Bad block Management 1) LOCKPRE is changed to PRE - Texts, Table and figures are changed. 2) Change Command set - Read A,B are changed to Read1. - Read C is changed to Read2. 3) Change AC, DC characterics
Preliminary
0.2
- tRB, tCRY, tCEH and tOH are added. 4) Correct Program time (max) - before : 700us - after : 500us 5) Edit figures - Address names are changed. 6) Change FBGA Package Dimension - FD1 : 1.70(before) -> 0.90(after)
Mar. 08. 2005 Preliminary
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Revision History
Revision No. History
1) Change AC Characteristics (1.8V device)
tRC before after 50 60 tRP 25 40 tREH 15 20 tWC 50 60 tWP 25 40 tWH 15 20 tREA 30 40
- Continued
Draft Date
Remark
2) Change AC Parameter 0.3
Before After tCRY(3.3V) 50+tr(R/B#) 60+tr(R/B#) tCRY(1.8V) 50+tr(R/B#) 80+tr(R/B#) tOH 15 10
Jul. 08. 2005
Preliminary
3) Change Figure 20,22 4) Add Read ID Table 5) Change PAD Configuration - GND is changed to VSS. 6) Add Marking Information 1) The test condition for ICC1 operating current is corrected.
tCRY(3.3V)
tRC=50ns, 0.4
Before CE#=VIL,
IOUT=0mA tRC(1.8V=60ns,
After 3.3V=50ns) CE#=VIL,
Jul. 15. 2005
Preliminary
IOUT=0mA
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Revision History
Revision No. History
1) The test conditions is corrected.
Test Conditions (ICC1) Test Conditions (ILI, ILO) VIN=VOUT=0 to 3.6V
- Continued
Draft Date
Remark
tRC=50ns,
Before CE#=VIL,
IOUT=0mA tRC(1.8V=60ns, 0.5
After 3.3V=50ns) CE#=VIL, VIN=VOUT=(1.8V, 0 to 1.95V) =(3.3V, 0 to 3.6V)
Jul. 20. 2005
Preliminary
IOUT=0mA 2) Change VIL parameter (max.)
1.8V Before After 0.2xVcc 0.4 3.3V 0.2xVcc 0.8
1) Correct the test Conditions (DC Characteristics table) Test Conditions (ILI, ILO)
Before VIN=VOUT=(1.8V, 0 to 1.95V) =(3.3V, 0 to 3.6V) VIN=VOUT=0 to Vcc (max)
0.6
After
Jul. 22. 2005
Preliminary
2) Change AC Conditions table 3) Add tWW parameter ( tWW = 100ns, min) - Texts & Figures are added. - tWW is added in AC timing characteristics table. 1) Edit Copy Back Program operation step 2) Edit System Interface Using CE don't care Figures. 3) Change AC Characteristics (3.3V device) 0.7
before after tRP 30 25 tREA 35 30
Aug. 01. 2005
Preliminary
4) Correct Address Cycle Map. 1) Correct PKG dimension (TSOP, USOP PKG) CP 0.8 Before After 0.9 0.050 0.100 Nov. 07. 2005 Preliminary Aug. 29. 2005 Preliminary
1) Correct USOP figure.
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Revision History
Revision No.
1.0 1.1 1.2 1) Delet Preliminary. 1) Correct Figure 32. 1) Add ECC algorithm. (1bit/512bytes) 2) Correct Read ID naming 1) Change AC Parameter
tWHR
- Continued
History
Draft Date
Nov. 08. 2005 Feb. 06. 2006 May. 09. 2006
Remark
1.3
Before After
60 ns 50 ns
Jun. 20. 2006
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash FEATURES SUMMARY
HIGH DENSITY NAND Flash MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities FAST BLOCK ERASE - Block erase time: 2ms (Typ.) STATUS REGISTER ELECTRONIC SIGNATURE - 1st cycle : Manufacturer Code - 2nd cycle: Device Code SUPPLY VOLTAGE - 3.3V device: VCC = 2.7 to 3.6V : HY27USXX121A CHIP ENABLE DON'T CARE - Simple interface with microcontroller AUTOMATIC PAGE 0 READ AT POWER-UP OPTION - Boot from NAND support - Automatic Memory Download SERIAL NUMBER OPTION HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions DATA INTEGRITY - 100,000 Program/Erase cycles (with 1bit/512byte ECC) - 10 years Data Retention PACKAGE - HY27(U/S)S(08/16)121A-T(P) : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - HY27(U/S)S(08/16)121A-T (Lead) - HY27(U/S)S(08/16)121A-TP (Lead Free) - HY27(U/S)S(08/16)121A-S(P) : 48-Pin USOP1 (12 x 17 x 0.65 mm) - HY27(U/S)S(08/16)121A-S (Lead) - HY27(U/S)S(08/16)121A-SP (Lead Free) - HY27(U/S)S(08/16)121A-F(P) : 63-Ball FBGA (9 x 11 x 1.0 mm) - HY27(U/S)S(08/16)121A-F (Lead) - HY27(U/S)S(08/16)121A-FP (Lead Free)
- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX121A Memory Cell Array = (512+16) Bytes x 32 Pages x 4,096 Blocks = (256+8) Words x 32 pages x 4,096 Blocks PAGE SIZE - x8 device : (512 + 16 spare) Bytes : HY27(U/S)S08121A - x16 device: (256 + 8 spare) Words : HY27(U/S)S16121A
BLOCK SIZE - x8 device: (16K + 512 spare) Bytes - x16 device: (8K + 256 spare) Words PAGE READ / PROGRAM - Random access: 3.3V: 12us (max.) 1.8V: 15us (max.) - Sequential access: 3.3V device: 50ns (min.) 1.8V device: 60ns (min.) - Page program time: 200us (typ.) COPY BACK PROGRAM MODE - Fast page copy without external buffering
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 1. SUMMARY DESCRIPTION
The HYNIX HY27(U/S)S(08/16)121A series is a 64Mx8bit with spare 2Mx8 bit capacity. The device is offered in 1.8V Vcc Power Supply and in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 4096 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected Flash cells. A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 16Kbyte(X8 device) block. Data in the page mode can be read out at 50ns cycle time(3.3V device) per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modifying can be lockde using the WP input pin. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. Even the write-intensive systems can take advantage of the HY27(U/S)S(08/16)121A extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. The chip could be offered with the CE don't care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up, Read ID2 extension. The HYNIX HY27(U/S)S(08/16)121A series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm, FBGA 9 x 11 mm.
1.1 Product List
PART NUMBER HY27SS08121A HY27SS16121A HY27US08121A HY27US16121A ORIZATION x8 x16 x8 x16 VCC RANGE 1.70 - 1.95 Volt 63FBGA / 48TSOP1 / 48USOP1 2.7V - 3.6 Volt PACKAGE
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8 IO7 - IO0 CLE ALE CE RE WE WP R/B Vcc Vss NC PRE
Data Input / Outputs (x16 Only) Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection Power-On Read Enable, Lock Unlock
Table 1: Signal Names
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 2. 48TSOP1 Contactions, x8 and x16 Device
Figure 3. 48USOP1 Contactions, x8 and x16 Device
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 4. 63FBGA Contactions, x8 Device (Top view through package)
Figure 5. 63FBGA Contactions, x16 Device (Top view through package)
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1.2 PIN DESCRIPTION
Pin Name IO0-IO7 IO8-IO15(1) Description DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CHIP ENABLE This input controls the selection of the device. When the device is busy CE low does not deselect the memory. WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. SUPPLY VOLTAGE The VCC supplies the power for all the operations (Read, Write, Erase). GROUND NO CONNECTION To Enable and disable the Lock mechanism and Power On Auto Read. When PRE is a logic high, Block Lock mode and Power-On Auto-Read mode are enabled, and when PRE is a logic low, Block Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on 3.3V device. Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it NC.
CLE
ALE
CE
WE
RE
WP R/B VCC VSS NC
PRE
Table 2: Pin Description
NOTE: 1. For x16 version only 2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25
IO1 A1 A10 A18 L
(1)
IO2 A2 A11 A19 L
(1)
IO3 A3 A12 A20 L
(1)
IO4 A4 A13 A21 L
(1)
IO5 A5 A14 A22 L
(1)
IO6 A6 A15 A23 L
(1)
IO7 A7 A16 A24 L(1)
Table 3: Address Cycle Map(x8)
NOTE: 1. L must be set to Low. 2. A8 is set to LOW or High by the 00h or 01h Command. IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25 IO1 A1 A10 A18 L(1) IO2 A2 A11 A19 L(1) IO3 A3 A12 A20 L(1) IO4 A4 A13 A21 L(1) IO5 A5 A14 A22 L(1) IO6 A6 A15 A23 L(1) IO7 A7 A16 A24 L(1) IO8-IO15 L(1) L(1) L(1) L(1)
Table 4: Address Cycle Map(x16)
NOTE: 1. L must be set to Low.
FUNCTION READ 1 READ 2 READ ID RESET PAGE PROGRAM COPY BACK PGM BLOCK ERASE READ STATUS REGISTER LOCK BLOCK LOCK TIGHT UNLOCK (start area) UNLOCK (end area) READ LOCK STATUS
1st CYCLE 00h/01h 50h 90h FFh 80h 00h 60h 70h 2Ah 2Ch 23h 24h 7Ah
2nd CYCLE 10h 8Ah D0h -
3rd CYCLE (10h) -
4th CYCLE
Acceptable command during busy
Yes
Yes
Table 5: Command Set
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
CLE H L H L L L L X X X X
ALE L H L H L L L X X X X
CE L L L L L L(1) L X X X H
WE Rising Rising Rising Rising Rising H H X X X X
RE H H H H H Falling H X X X X
WP X X H H H X X H H L 0V/Vcc Read Mode
MODE Command Input Address Input(4 cycles) Command Input Address Input(4 cycles)
Write Mode Data Input
Sequential Read and Data Output During Read (Busy) During Program (Busy) During Erase (Busy) Write Protect Stand By
Table 6: Mode Selection
NOTE: 1. With the CE high during latency time does not stop the read operation
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin must be high. See figure 7 and table 12 for details of the timings requirements. Command codes are always applied on IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. Four cycles are required to input the addresses for the 512Mbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 8 and table 12 for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/X16). In addition, addresses over the addressable space are disregarded even if the user sets them during command insertion.
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure 9 and table 12 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 10 to 14 and table 12 for details of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 3. DEVICE OPERATION
3.1 Page Read.
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with followed by the four address input cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available: random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes (x8 device) or 264 word (x16 device) of data within the selected page are transferred to the data registers in less than access random read time tR (12us, 3.3V device). The system controller can detect the completion of this data transfer tR (12us, 3.3V device) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting tR again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Writing the Read2 command user may selectively access the spare area of bytes 512 to 527. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row Read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command (00h/01h) is needed to move the pointer back to the main area. Figure_11 to 13 show typical sequence and timings for each read operation. Devices with automatic read of page0 at power up can be provided on request.
3.2 Page Program.
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 (x8 device), in a single page program cycle. The number of consecutive partial page programming operations within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes (x8 device) or 264 word (x16 device) of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to Figure_29. The data-loading sequence begins by inputting the Serial Data Input command (80h), followed by the four address input cycles and then serial data loading. The Page Program confirm command (10h) starts the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal P/ E/R Controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked Figure_17 The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. The block address loading is accomplished in two to four cycles depending on the device density. Only block addresses (A14 to A26) are needed while A9 to A13 is ignored. At the rising edge of WE after the erase confirm command input, the internal P/E/R Controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure_18 details the sequence.
3.4 Copy-Back Program.
The copy-back program is provided to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without using an external memory. Since the time-consuming sequential-reading and its reloading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is not needed to actually begin the programming operation. For backward-compatibility, issuing Program Confirm command during copy-back does not affect correct device operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Plane address must be the same between source and target page "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation." Figure 17 shows the command sequence for the copy-back operation. The Copy Back Program operation requires three steps: - 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 4 cycle bus to input the source page address.) This operation copies all 264 Words/ 528 Bytes from the page into the page Buffer. - 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 4cycles to input the target page address. A14 & A25 must be the same for the Source and Target Pages. - 3. Then the confirm command is issued to start the P/E/R Controller.
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operation is com pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 13 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command (00h or 50h) should be given before sequential page read cycle.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacturer code (ADh), the device code. The command register remains in Read ID mode until further commands are issued to it. Figure 19 shows the operation sequence, while tables 16 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when WP is high. Refer to table 12 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to figure 25.
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 4. OTHER FEATURES
4.1 Data Protection & Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V (1.8V device), 2.0V (3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in Figure 26. The two-step command sequence for program/erase provides additional software protection. If the power is dropped during the ready read/write/erase operation, Power protection function may not guaranteed the data. Power protection function is only available during the power on/off sequence.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Fig 27). Its value can be determined by the following guidance.
4.3 Lock Block Feature
In high state of PRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is regarded as NAND Flash without PRE pin. Block Lock mode is enabled while PRE pin state is high, which is to offer protection features for NAND Flash data. The Block Lock mode is divided into Unlock, Lock, Lock-tight operation. Consecutive blocks protects data allows those blocks to be locked or lock-tighten with no latency. This block lock scheme offers two levels of protection. The first allows software control (command input method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control (WP low pulse input method) before locking can be changed that is useful for protecting infrequently changed code blocks. The followings summarized the locking functionality. - All blocks are in a locked state on power-up. Unlock sequence can unlock the locked blocks. - The Lock-tight command locks blocks and prevents from being unlocked. Lock-tight state can be returned to lock state only by Hardware control(WP low pulse input). 1. Block lock operation 1) Lock - Command Sequence: Lock block Command (2Ah). See Fig. 20. - All blocks default to locked by power-up and Hardware control (WP low pulse input) - Partial block lock is not available; Lock block operation is based on all block unit - Unlocked blocks can be locked by using the Lock block command, and a lock block's status can be changed to unlock or lock-tight using the appropriate commands - On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY)
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
2) Unlock - Command Sequence: Unlock block Command (23h) + Start block address + Command (24h) + End block address. See Fig. 21. - Unlocked blocks can be programmed or erased. - An unlocked block's status can be changed to the locked or lock-tighten state using the appropriate sequence of commands. - Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available. - Start block address must be nearer to the logical LSB (Least Significant Bit) than End block address. - One block is selected for unlocking block when Start block address is same as End block address. 3) Lock-tight - Command Sequence: Lock-tight block Command (2Ch). See Fig. 22. - Lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. A block that is lock-tighten can't have its state changed by software control, only by hardware control (WP low pulse input); Unlocking multi area is not available - Only locked blocks can be lock-tighten by lock-tight command. - On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY) 4) Lock Block Boundaries after Unlock Command issuing - If Start Block address = 0000h and End Block Address = FFFFh , the device is all unlocked - If Start Block address = End Block Address = FFFFh , the device is all locked except for the last Block - If Start Block address = End Block Address = 0000h , the device is all locked except for the first Block 2. Block lock Status Read Block Lock Status can be read on a block basis to find out whether designated block is available to be programmed or erased. After writing 7Ah command to the command register and block address to be checked, a read cycle outputs the content of the Block Lock Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. RE or CE does not need to be toggled for updated status. Block Lock Status Read is prohibited while the device is busy state. Refer to table 15 for specific Status Register definitions. The command register remains in Block Lock Status Read mode until further commands are issued to it. In high state of PRE pin, write protection status can be checked by Block Lock Status Read (7Ah) while in low state by Status Read (70h).
4.4 Power-On Auto-Read
The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto- page read function. Auto-page read function is enabled only when PRE pin is logic high state. Serial access may be done after power-on without latency. Power-On Auto Read mode is available only on 3.3V device.
Rev 1.3 / Jun. 2006
18
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Parameter Valid Block Number
Symbol NVB
Min 4016
Typ
Max 4096
Unit Blocks
Table 6: Valid Blocks Number
NOTE: 1. The 1st block is guaranteed to be a valid block up to 1K cycles without ECC. (1bit/512bytes)
Symbol
Parameter Ambient Operating Temperature (Commercial Temperature Range)
Value 1.8V 0 to 70 -25 to 85 -40 to 85 -50 to 125 -65 to 150 -0.6 to 2.7 -0.6 to 2.7 3.3V 0 to 70 -25 to 85 -40 to 85 -50 to 125 -65 to 150 -0.6 to 4.6 -0.6 to 4.6
Unit V V
TA
Ambient Operating Temperature (Extended Temperature Range) Ambient Operating Temperature (Industrial Temperature Range)
TBIAS TSTG VIO(2) Vcc
Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage
Table 7: Absolute maximum ratings
NOTE: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
Rev 1.3 / Jun. 2006
19
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 6: Block Diagram
Rev 1.3 / Jun. 2006
20
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Parameter Sequential Read Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B) Symbol Test Conditions tRC(1.8V=60ns, 3.3V=50ns) CE=VIL, IOUT=0mA CE=VIH, WP=PRE=0V/Vcc CE=Vcc-0.2, WP=PRE=0V/Vcc VIN=0 to Vcc (max) VOUT =0 to Vcc (max) IOH=-100uA IOH=-400uA IOL=100uA IOL=2.1mA VOL=0.2V VOL=0.4V 1.8Volt Min Vcc-0.4 -0.3 Vcc-0.1 3 Typ 8 8 8 10 4 Max 15 15 15 1 50 10 10 Vcc+0. 3 0.4 0.1 Min 2 -0.3 2.4 8 10 10 3.3Volt Typ 10 10 10 Max 20 20 20 1 50 10 10 Vcc+0 .3 0.8 0.4 Unit
Operating Current
ICC1 ICC2 ICC3 ICC4 ICC5 ILI ILO VIH VIL VOH VOL IOL (R/B)
mA mA mA mA uA uA uA V V V V V V mA mA
Table 8: DC and Operating Characteristics
Value 1.8Volt 0V to Vcc 5ns Vcc / 2 1 TTL GATE and CL=30pF 3.3Volt 0.4V to 2.4V 5ns 1.5V 1 TTL GATE and CL=50pF 1 TTL GATE and CL=100pF
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (1.7V - 1.95Volt & 2.7V - 3.3V) Output Load (3.0V - 3.6V)
Table 9: AC Conditions
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Item Input / Output Capacitance Input Capacitance
Symbol CI/O CIN
Test Condition VIL=0V VIN=0V
Min -
Max 10 10
Unit pF pF
Table 10: Pin Capacitance (TA=25C, F=1.0MHz)
Parameter Program Time Dummy Busy Time for the Lock or Lock-tight Block Number of partial Program Cycles in the same page Block Erase Time Main Array Spare Array
Symbol tPROG tLBSY NOP NOP tBERS
Min -
Typ 200 5 2
Max 500 10 1 2 3
Unit us us Cycles Cycles ms
Table 11: Program / Erase Characteristics
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Parameter
CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output High Z CE High to Output High Z RE or CE high to Output hold RE High Hold Time Output High Z to RE low CE Access Time WE High to RE low Last RE High to busy (at sequential read) CE High to Ready (in case of interception by CE at read) CE High Hold Time (at the last serial read)
(3)
Symbol
tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tR tAR tCLR tRR tRP tWB tRC tREA tRHZ tCHZ tOH tREH tIR tCEA tWHR
1.8Volt Min
0 10 0 10 40 0 10 20 10 60 20 15 10 10 20 40 100 60 40 30 20 10 20 0 45 50 100
80+tr(R/B#)
(4)
3.3Volt Min
0 10 0 10 25
(1)
Max
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns
0 10 20 10 50 15 12 10 10 20 25 100 50 30 30 20 10 15 0 45 50 100
60+tr(R/B#)
(4)
us ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRB tCRY tCEH
tRST tWW(5) 100 100
100
5/10/500(2) 5/10/500(2)
Device Resetting Time (Read / Program / Erase) Write Protection time
us ns
100
Table 12: AC Timing Characteristics
NOTE:
1. If tCS is less than 10ns tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. 2. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us 3. To break the sequential read cycle, CE must be held for longer time than tCEH. 4. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 5. Program / Erase Enable Operation : WP high to WE High. Program / Erase Disable Operation : WP Low to WE High.
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
IO 0 1 2 3 4 5 6 7
Pagae Program Pass / Fail NA NA NA NA Ready/Busy Ready/Busy Write Protect
Block Erase Pass / Fail NA NA NA NA Ready/Busy Ready/Busy Write Protect
Read NA NA NA NA NA Ready/Busy Ready/Busy Write Protect
CODING Pass: `0' Fail: `1' Pass: `0' Fail: `1' (Only for Cache Program, else Don't care) Active: `0' Idle: `1' Busy: `0' Ready': `1' Protected: `0' Not Protected: `1'
Table 13: Status Register Coding
DEVICE IDENTIFIER CYCLE 1st 2nd
DESCRIPTION Manufacturer Code Device Identifier
Table 14: Device Identifier Coding
Part Number HY27US08121A HY27US16121A HY27SS08121A HY27SS16121A
Voltage 3.3V 3.3V 1.8V 1.8V
Bus Width X8 X16 X8 X16
1st cycle (Manufacture Code) ADh ADh ADh ADh
2nd cycle (Device Code) 76h 56h 36h 46h
Table 15: Read ID Table
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 16: Lock Status Code
Figure 7: Command Latch Cycle
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 8: Address Latch Cycle
Rev 1.3 / Jun. 2006
26
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 9. Input Data Latch Cycle
tCEA
CE
tREA tREH tRP tCHZ* tREA tREA tOH
RE
tRHZ tRHZ* tOH Dout
I/Ox
tRR
Dout tRC
Dout
R/B
Notes : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
Figure 10: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 11: Status Read Cycle
Figure 12: Read1 Operation (Read One Page)
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 13: Read1 Operation intercepted by CE
Figure 14: Read2 Operation (Read One Page)
Rev 1.3 / Jun. 2006 29
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 15: Sequential Row Read Operation Within a Block
Rev 1.3 / Jun. 2006
30
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 16: Page Program Operation
Rev 1.3 / Jun. 2006
31
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 17 : Copy Back Program
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 18: Block Erase Operation (Erase One Block)
CLE CE WE
tAR
ALE RE
tREA
I/O x
90h
Read ID Command
00h
Address 1 cycle
ADh
76h
Maker Code Device Code
Figure 19: Read ID Operation
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 20: Lock Command
Figure 21: Unlock Command Sequence
Rev 1.3 / Jun. 2006
34
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 22: Lock Tight Command
Figure 23: Lock Status Read Timing
Rev 1.3 / Jun. 2006
35
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
1.8V Vcc WE CE ALE CLE
tR
R/B PRE RE I/Ox
Data1 Data2 Data3 Last Data
Data Output
Figure 24: Automatic Read at Power On
Figure 25: Reset Operation
Rev 1.3 / Jun. 2006 36
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 26: Power On/Off Timing
VTH = 1.5 Volt for 1.8 Volt Supply devices; 2.5 Volt for 3.3 Volt Supply devices
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 27: Ready/Busy Pin electrical specifications
Rev 1.3 / Jun. 2006
38
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 28: Lock/Unlock FSM Flow Cart
Figure 29: Pointer operations
Rev 1.3 / Jun. 2006
39
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 30: Pointer Operations for porgramming
Rev 1.3 / Jun. 2006
40
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
System Interface Using CE don't care To simplify system interface, CE may be inactive during data loading or sequential data-reading as shown below. So, it is possible to
connect NAND Flash to a microprocessor. The only function that was removed from standard NAND Flash to make CE don't care read operation was disabling of the automatic sequential read function.
Figure 31: Program Operation with CE don't-care.
Figure 32: Read Operation with CE don't-care.
Rev 1.3 / Jun. 2006 41
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 6th Byte/ 3rd Word in the spare area of the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 20. The 1st block, which is placed on 00h block address is guaranteed to be a valid block. Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block.
See the "Copy Back Program" section for more details.
Refer to Table 17 for the recommended procedure to follow if an error occurs during an operation. Operation Erase Program Read Recommended Procedure Block Replacement Block Replacement or ECC (with 1bit/512byte) ECC (with 1bit/512byte)
Table 17: Block Failure
Figure 33: Bad Block Management Flowchart
Rev 1.3 / Jun. 2006 42
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 34~37)
Figure 34: Enable Programming
Figure 35: Disable Programming
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 36: Enable Erasing
Figure 37: Disable Erasing
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 38: 48-pin TSOP1, 12 x 20mm, Package Outline
millimeters
Min Typ Max 1.200 0.050 0.980 0.170 0.100 0.150 1.030 0.250 0.200 0.100 11.910 19.900 18.300 12.000 20.000 18.400 0.500 0.500 0 0.680 5 12.120 20.100 18.500
Symbol A A1 A2 B C CP D E E1 e L alpha
Table 18: 48-pin TSOP1, 12 x 20mm, Package Mechanical Data
Rev 1.3 / Jun. 2006
45
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 39. 48-pin USOP1, 12 x 17mm, Package Outline
Symbol A A1 A2 B C C1 CP D D1 E e alpha
millimeters
Min 0 0.470 0.130 0.065 0.450 16.900 11.910 15.300 0 Typ 0.050 0.520 0.160 0.100 0.650 17.000 12.000 15.400 0.500 8 Max 0.650 0.080 0.570 0.230 0.175 0.750 0.100 17.100 12.120 15.500
Table 19: 48-pin USOP1, 12 x 17mm, Package Mechanical Data
Rev 1.3 / Jun. 2006
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HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Figure 40. 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Outline
NOTE: Drawing is not to scale.
Symbol A A1 A2 b D D1 D2 E E1 E2 e FD FD1 FE FE1 SD SE
Millimeters
Min 0.80 0.25 0.55 0.40 8.90 Typ 0.90 0.30 0.60 0.45 9.00 4.00 7.20 11.00 5.60 8.80 0.80 2.50 0.90 2.70 1.10 0.40 0.40 Max 1.00 0.35 0.65 0.50 9.10
10.90
11.10
Table 20: 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Mechanical Data
Rev 1.3 / Jun. 2006 47
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash MARKING INFORMATION - TSOP1/USOP
Packag M a r k in g E x a m p le
K
O
R
TSOP1 / USOP
H
Y
2
7
x
S
x
x
1
2
X
A
x
x
x
x
Y
W
W
x
x
- h y n ix - KOR - H Y27xSxx12xA xxxx H Y : H Y N IX 2 7 : N A N D F la s h x : P o w e r S u p p ly S : C la s s ific a tio n x x : B it O r g a n iz a tio n 1 2 : D e n s ity x: M ode A : V e r s io n x : Package T ype x : P a c k a g e M a te r ia l x : O p e r a tin g T e m p e r a tu r e x : B a d B lo c k
: H y n ix S y m b o l : O r ig in C o u n tr y : P a rt N u m b e r
: U ( 2 .7 V ~ 3 .6 V ) , L ( 2 .7 V ) , S ( 1 .8 V ) : S in g le L e v e l C e ll+ S in g le D ie + S m a ll B lo c k : 0 8 (x8 ), 1 6 (x1 6 ) : 5 1 2 M b it : 1 ( 1 n C E & 1 R / n B ; S e q u e n tia l R o w R e a d e n a b le ) 2 ( 1 n C E & 1 R / n B ; S e q u e n tia l R o w R e a d D is a b le ) : 2 n d G e n e r a tio n : T (4 8 -T S O P 1 ), S (4 8 -U S O P ) : B la n k ( N o r m a l) , P ( L e a d F r e e ) : C (0 ~ 7 0 ), E (-2 5 ~ 8 5 ) M (-3 0 ~ 8 5 ), I(-4 0 ~ 8 5 ) : B ( I n c lu d e d B a d B lo c k ) , S ( 1 ~ 5 B a d B lo c k ) , P ( A ll G o o d B lo c k )
- Y : Y e a r (e x: 5 = ye a r 2 0 0 5 , 0 6 = ye a r 2 0 0 6 ) - w w : W o rk W e e k (e x : 1 2 = w o rk w e e k 1 2 ) - x x : P ro c e ss C o d e N o te - C a p it a l L e t t e r - S m a ll L e t t e r : F ix e d I te m : N o n - fix e d I te m
Rev 1.3 / Jun. 2006
48
HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash MARKING INFORMATION - FBGA
P a ck a g M a rk in g E x a m p le
K
O x
R A
FBGA
H
Y
2
7
x
S
x
x
1
2
x
x
x
x
Y
W
W
x
x
- h y n ix - KOR - H Y27xSxx12xA xxxx H Y : H Y N IX 2 7 : N A N D F lash x : P o w e r S u p p ly S : C la ssifica tio n x x : B it O rg an izatio n 1 2 : D e n sity x: M ode A : V e rsio n x : P acka g e T yp e x : P acka g e M a te ria l x : O p e ra tin g T e m p eratu re x : B a d B lo ck
: H y n ix S y m b o l : O rig in C o u n try : P a rt N u m b er
: U (2 .7 V ~ 3 .6 V ), L (2 .7 V ), S (1 .8 V ) : S in g le Le v el C ell+ S in g le D ie+ S m all B lo ck : 0 8 (x 8 ), 1 6 (x1 6 ) : 5 1 2 M b it : 1 (1 n C E & 1 R /n B ; S e q u e n tia l R o w R ea d E n a b le ) 2 (1 n C E & 1 R /n B ; S e q u e n tial R o w R e a d D isa b le ) : 2 n d G e n eration : F (6 3 F B G A ) : B lan k (N o rm a l), P (Le a d Free ) : C (0 ~ 7 0 ), E (-2 5 ~ 8 5 ) M (-3 0 ~ 8 5 ), I(-4 0 ~ 8 5 ) : B (In clu d e d B a d B lo ck ), S (1 ~ 5 B a d B lo ck ), P (A ll G o o d B lo ck )
- Y : Y e a r (e x: 5 = y ea r 2 0 0 5 , 0 6 = y ea r 2 0 0 6 ) - w w : W o rk W e ek (e x : 1 2 = w o rk w e e k 1 2 ) - x x : P ro ce ss C o d e N o te - C a p ita l L e tte r - S m a ll L e tte r : F ixed Item : N o n -fixe d Ite m
49
Rev 1.3 / Jun. 2006

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